In automatic circuit testers for testing random access memories (RAMs) or logic including RAMs, digital test patterns (multibit words for both the address and data) are provided at high speed (e.g., up to 50 MHz) to the address and data pins of a memory under test (MUT); the MUT is read, and the outputs are compared with the inputs. Failures are stored in a fail map RAM (also referred to as a catch RAM) having addresses that correspond to the addresses of the MUT. After testing, the computer reads the fail map RAM one word at a time, and uses the failure information, e.g, to identify the topical location of the failed memory elements to attempt to correlate the failures to processinq of the memories or to replace failed memory elements with redundant elements. The errors in the fail map RAM are also sometimes counted, and in some instances the high-speed pattern generator has been used to scan the fail map RAM at high speed in counting errors.
Sequences of addresses often do not correspond to the topical locations in the memories, and bits of multibit words may be read in different order for different addresses, requiring that there be further analysis of the failure information in the fail map RAM, using software, to present the failure information in a desired format to provide useful information. Software has also been used to compress the failure information to indicate that there is at least one failure in a group of memory elements. The group can then be analyzed further to identify the precise failed element.